Invention Grant
US08524592B1 Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices
有权
形成具有自对准触点和低k间隔物的半导体器件的方法以及所得到的器件
- Patent Title: Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices
- Patent Title (中): 形成具有自对准触点和低k间隔物的半导体器件的方法以及所得到的器件
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Application No.: US13584055Application Date: 2012-08-13
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Publication No.: US08524592B1Publication Date: 2013-09-03
- Inventor: Ruilong Xie , Xiuyu Cai, Jr. , Kangguo Cheng , Ali Khakifirooz
- Applicant: Ruilong Xie , Xiuyu Cai, Jr. , Kangguo Cheng , Ali Khakifirooz
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763

Abstract:
One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.
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