Invention Grant
- Patent Title: Arrangement for solder bump formation on wafers
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Application No.: US13135970Application Date: 2011-07-19
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Publication No.: US08524593B2Publication Date: 2013-09-03
- Inventor: Chunghsin Lee , Jian Zhang
- Applicant: Chunghsin Lee , Jian Zhang
- Applicant Address: US MA Wakefield
- Assignee: Semigear Inc
- Current Assignee: Semigear Inc
- Current Assignee Address: US MA Wakefield
- Agent Don Halgren
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.
Public/Granted literature
- US20120289042A1 Arrangement for solder bump formation on wafers Public/Granted day:2012-11-15
Information query
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