Invention Grant
- Patent Title: Laminated chips package, semiconductor substrate and method of manufacturing the laminated chips package
- Patent Title (中): 层叠芯片封装,半导体衬底及其制造方法
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Application No.: US12588713Application Date: 2009-10-26
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Publication No.: US08525167B2Publication Date: 2013-09-03
- Inventor: Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
- Applicant: Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
- Applicant Address: US CA Milpitas CN Hong Kong
- Assignee: Headway Technologies, Inc.,SAE Magnetics (H.K.) Ltd.
- Current Assignee: Headway Technologies, Inc.,SAE Magnetics (H.K.) Ltd.
- Current Assignee Address: US CA Milpitas CN Hong Kong
- Agency: Oliff & Berridge, PLC
- Main IPC: H01L23/522
- IPC: H01L23/522

Abstract:
In a laminated chip package, a plurality of semiconductor plates each having a semiconductor device and a wiring electrode connected to the semiconductor device are laminated. On a side surface for wiring of the laminated chip package, an end face of an inner electrode for examination formed inside the side surface for wiring in the semiconductor plate is formed. The laminated chip package further has an outer electrode for examination connecting the end faces of the inner electrodes for examination along a lamination direction of the semiconductor plates, only for two adjacent semiconductor plates among the semiconductor plates.
Public/Granted literature
- US20110095289A1 Laminated chips package, semiconductor substrate and method of manufacturing the laminated chips package Public/Granted day:2011-04-28
Information query
IPC分类: