Invention Grant
- Patent Title: Semiconductor structure with improved channel stack and method for fabrication thereof
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Application No.: US13039986Application Date: 2011-03-03
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Publication No.: US08525271B2Publication Date: 2013-09-03
- Inventor: Paul E. Gregory , Lucian Shifren , Pushkar Ranade
- Applicant: Paul E. Gregory , Lucian Shifren , Pushkar Ranade
- Applicant Address: US CA Los Gatos
- Assignee: SuVolta, Inc.
- Current Assignee: SuVolta, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Baker Botts L.L.P.
- Main IPC: H01L21/70
- IPC: H01L21/70

Abstract:
A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer.
Public/Granted literature
- US20120223389A1 SEMICONDUCTOR STRUCTURE WITH IMPROVED CHANNEL STACK AND METHOD FOR FABRICATION THEREOF Public/Granted day:2012-09-06
Information query
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