Invention Grant
US08525319B2 Selecting chips within a stacked semiconductor package using through-electrodes
有权
使用贯通电极选择堆叠半导体封装内的芯片
- Patent Title: Selecting chips within a stacked semiconductor package using through-electrodes
- Patent Title (中): 使用贯通电极选择堆叠半导体封装内的芯片
-
Application No.: US12981443Application Date: 2010-12-29
-
Publication No.: US08525319B2Publication Date: 2013-09-03
- Inventor: Bok Gyu Min , Kyoung Sook Park , Da Un Nah
- Applicant: Bok Gyu Min , Kyoung Sook Park , Da Un Nah
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Patent Ltd.
- Priority: KR10-2010-0042454 20100506
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A stacked semiconductor package includes first and second semiconductor chips including semiconductor chip bodies which have circuit units, first through-electrodes which pass through the semiconductor chip bodies at first positions, and second through-electrodes which pass through the semiconductor chip bodies at second positions and provide a chip enable signal to the circuit units. A spacer including a spacer body may be interposed between the first semiconductor chip and the second semiconductor chip, with an inverter chip embedded in the spacer body. Wiring patterns formed on the spacer body may connect the first through-electrodes of the first semiconductor chip with the second through-electrodes of the second semiconductor chip, the first through-electrodes of the first semiconductor chip with input terminals of the inverter chip, and output terminals of the inverter chip with the second through-electrodes of the first semiconductor chip.
Public/Granted literature
- US20110272804A1 SELECTING CHIPS WITHIN A STACKED SEMICONDUCTOR PACKAGE USING THROUGH-ELECTRODES Public/Granted day:2011-11-10
Information query
IPC分类: