Invention Grant
- Patent Title: Conductive chip disposed on lead semiconductor package
- Patent Title (中): 导电芯片设置在引线半导体封装上
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Application No.: US13177060Application Date: 2011-07-06
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Publication No.: US08525321B2Publication Date: 2013-09-03
- Inventor: Jatinder Kumar , David Chong
- Applicant: Jatinder Kumar , David Chong
- Applicant Address: US CA San Jose
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Agency: Brake Hughes Bellermann LLP
- Main IPC: H01L23/24
- IPC: H01L23/24
Abstract:
In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.
Public/Granted literature
- US20130009309A1 CONDUCTIVE CHIP DISPOSED ON LEAD SEMICONDUCTOR PACKAGE AND METHODS OF MAKING THE SAME Public/Granted day:2013-01-10
Information query
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