Invention Grant
- Patent Title: Chip with sintered connections to package
- Patent Title (中): 芯片与烧结连接到封装
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Application No.: US13154778Application Date: 2011-06-07
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Publication No.: US08525338B2Publication Date: 2013-09-03
- Inventor: Hiroaki Sato , Kiyoaki Hashimoto , Yoshikuni Nakadaira , Norihito Masuda , Belgacem Haba , Ilyas Mohammed , Philip Damberg
- Applicant: Hiroaki Sato , Kiyoaki Hashimoto , Yoshikuni Nakadaira , Norihito Masuda , Belgacem Haba , Ilyas Mohammed , Philip Damberg
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/00

Abstract:
A microelectronic package and method of making same are provided. The package includes a substrate having first and second opposed surfaces, an edge surface extending therebetween, a plurality of terminals, and a plurality of conductive elements electrically connected with the terminals. The edge surface can be disposed at a periphery of the substrate or can be the edge surface of an aperture within the substrate. A microelectronic element has a front face and contacts thereon, with at least some of the contacts being adjacent to the edge surface of the substrate. A dielectric material overlies the edge surface of the substrate and defines a sloping surface between the front face of the microelectronic element and the substrate. A conductive matrix material defines a plurality of conductive interconnects extending along the sloping surface. The conductive interconnects electrically interconnect respective ones of the contacts with the conductive elements.
Public/Granted literature
- US20120313264A1 CHIP WITH SINTERED CONNECTIONS TO PACKAGE Public/Granted day:2012-12-13
Information query
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