Invention Grant
- Patent Title: Wiring substrate, manufacturing method thereof, and semiconductor package
- Patent Title (中): 接线基板，其制造方法和半导体封装
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Application No.: US12968405Application Date: 2010-12-15
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Publication No.: US08525356B2Publication Date: 2013-09-03
- Inventor: Junichi Nakamura , Kazuhiro Kobayashi
- Applicant: Junichi Nakamura , Kazuhiro Kobayashi
- Applicant Address: JP Nagano
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano
- Agency: IPUSA,PLLC
- Priority: JP2010-005017 20100113
- Main IPC: H01L23/544
- IPC: H01L23/544
Abstract:
A disclosed wiring substrate includes an insulating layer, a recess formed on a surface of the insulating layer, and an alignment mark formed inside of the recess, wherein a face of the alignment mark is roughened, recessed from the surface of the insulating layer, and exposed from the recess.
Public/Granted literature
- US20110169164A1 WIRING SUBSTRATE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE Public/Granted day:2011-07-14
Information query
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