Invention Grant
- Patent Title: Non-volatile semiconductor memory device capable of improving failure-relief efficiency
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Application No.: US13242902Application Date: 2011-09-23
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Publication No.: US08526241B2Publication Date: 2013-09-03
- Inventor: Masanobu Shirakawa
- Applicant: Masanobu Shirakawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2011-004953 20110113
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04 ; G11C16/06 ; G11C8/00

Abstract:
According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong.
Public/Granted literature
- US20120182803A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IMPROVING FAILURE-RELIEF EFFICIENCY Public/Granted day:2012-07-19
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