Invention Grant
US08526255B1 Method and apparatus for memory test 有权
用于记忆测试的方法和装置

Method and apparatus for memory test
Abstract:
Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a scrambler configured to provide a driving address and associated data to an envelope based on a memory configuration for using a memory array. The driving address and the associated data are used to test the memory array according to a test pattern. The envelope is configured to translate the driving address into a corresponding physical address of the memory array based on the memory configuration.
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