Invention Grant
US08527821B2 Hybrid test compression architecture using multiple codecs for low pin count and high compression devices
有权
混合测试压缩架构使用多个编解码器用于低引脚数和高压缩设备
- Patent Title: Hybrid test compression architecture using multiple codecs for low pin count and high compression devices
- Patent Title (中): 混合测试压缩架构使用多个编解码器用于低引脚数和高压缩设备
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Application No.: US12758954Application Date: 2010-04-13
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Publication No.: US08527821B2Publication Date: 2013-09-03
- Inventor: Malav Shrikant Shah , Swathi Gangasani , Srivaths Ravi
- Applicant: Malav Shrikant Shah , Swathi Gangasani , Srivaths Ravi
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
This invention uses multiple codecs to efficiently achieve the right balance between compression and coverage for a given design. This application illustrates a simple example using two codecs including a high compression codec and a low compression codec. The test engineer generates a first set of test patterns using the high compression codec. If this high compression results in unacceptable fault coverage loss, the top-up patterns for additional coverage are generated using the low compression codec. The invention may use multiple codecs serially one after the other. The codecs can be of different types or parameters (such as compression ratio, debug tolerance and combinational codec versus sequential codec).
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