A controller is used for an electronic memory device which has multi-level cell (MLC) memory elements. The individual MLC memory elements are capable of storing at least two bits. The controller includes a physical interface to couple the controller to the electronic memory device. The controller also includes a processing unit coupled to the physical interface. The processing unit operates the electronic memory device using a restricted number of programming states for a single data bit. The restricted number of programming states includes first and second states used to represent a most significant bit (MSB) of the at least two bits of data of the designated programming states.