Invention Grant
- Patent Title: Layout technique for stress management cells
- Patent Title (中): 压力管理细胞布局技术
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Application No.: US13237365Application Date: 2011-09-20
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Publication No.: US08527933B2Publication Date: 2013-09-03
- Inventor: Puneet Sharma
- Applicant: Puneet Sharma
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
An integrated circuit device layout is created based on charge carrier mobility characteristics of the device's non-functional cells. The charge carrier mobility of the non-functional cells can alter behavioral characteristics such as the hold time, setup time, or leakage current of nearby functional logic cells. Accordingly, a layout tool creates the layout for the integrated circuit device by selecting and placing non-functional cells having different mobility so as to selectively alter the characteristics of nearby logic cells.
Public/Granted literature
- US20130074026A1 LAYOUT TECHNIQUE FOR STRESS MANAGEMENT CELLS Public/Granted day:2013-03-21
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