Invention Grant
- Patent Title: ETSOI CMOS with back gates
- Patent Title (中): 带后门的ETSOI CMOS
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Application No.: US13611656Application Date: 2012-09-12
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Publication No.: US08530287B2Publication Date: 2013-09-10
- Inventor: Jin Cai , Robert H Dennard , Ali Khakifirooz
- Applicant: Jin Cai , Robert H Dennard , Ali Khakifirooz
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Harrington & Smith
- Main IPC: H01L21/84
- IPC: H01L21/84

Abstract:
A method to fabricate a structure includes providing a silicon-on-insulator wafer, implanting through a semiconductor layer and an insulating layer a functional region having a first type of conductivity to be adjacent to a top surface of the substrate; implanting within the functional region through the semiconductor layer and the insulating layer an electrically floating back gate region having a second type of conductivity; forming isolation regions in the semiconductor layer; forming first and second transistor devices to have the same type of conductivity over the semiconductor layer such that one of the transistor devices overlies the implanted back gate region and the other one of the transistor devices overlies only the underlying top surface of the functional region not overlapped by the implanted back gate region; and providing an electrical contact to the functional region for applying a bias voltage.
Public/Granted literature
- US20130005095A1 ETSOI CMOS With Back Gates Public/Granted day:2013-01-03
Information query
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