Invention Grant
US08530301B2 MOS device with substrate potential elevation for ESD protection
有权
具有ESD保护的衬底电位提升的MOS器件
- Patent Title: MOS device with substrate potential elevation for ESD protection
- Patent Title (中): 具有ESD保护的衬底电位提升的MOS器件
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Application No.: US12951255Application Date: 2010-11-22
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Publication No.: US08530301B2Publication Date: 2013-09-10
- Inventor: Gianluca Boselli , Charvaka Duvvury
- Applicant: Gianluca Boselli , Charvaka Duvvury
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/8238
- IPC: H01L21/8238
Abstract:
An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region. The terminal of the functional circuit (24, PAD) is coupled to the cathode (36) of the Nwell diode, and the anode (37) of the Nwell diode is connected in series with a path from the drain (44) to the source (43) of the NMOS transistor (200).
Public/Granted literature
- US20110063765A1 MOS DEVICE WITH SUBSTRATE POTENTIAL ELEVATION FOR ESD PROTECTION Public/Granted day:2011-03-17
Information query
IPC分类:
