Invention Grant
US08530326B2 Method of fabricating a dummy gate structure in a gate last process
有权
在门最后工艺中制造虚拟栅极结构的方法
- Patent Title: Method of fabricating a dummy gate structure in a gate last process
- Patent Title (中): 在门最后工艺中制造虚拟栅极结构的方法
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Application No.: US13538220Application Date: 2012-06-29
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Publication No.: US08530326B2Publication Date: 2013-09-10
- Inventor: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng-Cheng , Chien-Hung Wu , Tzung-Chi Lee
- Applicant: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng-Cheng , Chien-Hung Wu , Tzung-Chi Lee
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/76
- IPC: H01L21/76
Abstract:
A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
Public/Granted literature
- US20120270379A1 METHOD OF FABRICATING A DUMMY GATE STRUCTURE IN A GATE LAST PROCESS Public/Granted day:2012-10-25
Information query
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