Invention Grant
- Patent Title: Semiconductor package and fabrication method
- Patent Title (中): 半导体封装及制造方法
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Application No.: US12905540Application Date: 2010-10-15
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Publication No.: US08530351B2Publication Date: 2013-09-10
- Inventor: Junichi Nakamura
- Applicant: Junichi Nakamura
- Applicant Address: JP Nagano
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano
- Agency: Locke Lord LLP
- Priority: JP2004-364983 20041216; JP2005-214904 20050725
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board (20) including a plurality of insulating resin layers, semiconductor element-mounting terminals (18) formed on the uppermost surface of the board, and external connection terminals (12) formed on the bottom surface thereof. Each external connection terminal (12) is formed as a bump projected downward from the bottom surface of the package, and each bump is filled with the insulating resin (14) while the surface thereof is covered by a metal (16). Wiring (24), (26) including a conductor via (26a) electrically connect the metal of the metal layer 16 and the semiconductor element-mounting terminals (18).
Public/Granted literature
- US20110034022A1 SEMICONDUCTOR PACKAGE AND FABRICATION METHOD Public/Granted day:2011-02-10
Information query
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