Invention Grant
- Patent Title: Method for selectively forming crystalline silicon layer regions above gate electrodes
- Patent Title (中): 选择性地形成栅电极之上的晶体硅层区的方法
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Application No.: US13495387Application Date: 2012-06-13
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Publication No.: US08530900B2Publication Date: 2013-09-10
- Inventor: Mitsutaka Matsumoto , Yuta Sugawara
- Applicant: Mitsutaka Matsumoto , Yuta Sugawara
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Greenblum & Bernstein, P.L.C.
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/088

Abstract:
Preparing a substrate; forming a plurality of gate electrodes above the substrate; forming a gate insulating layer above the gate electrodes; forming an amorphous silicon layer above the gate insulating layer; forming crystalline silicon layer regions by irradiating the amorphous silicon layer in regions above the gate electrodes with a laser beam having a wavelength from 473 nm to 561 nm so as to crystallize the amorphous silicon layer in the regions above the gate electrodes, and forming an amorphous silicon layer region in a region other than the regions above the gate electrodes; and forming source electrodes and drain electrodes above the crystalline silicon layer regions are included, and a thickness of the gate insulating layer and a thickness of the amorphous silicon layer satisfy predetermined expressions.
Public/Granted literature
- US20130134431A1 THIN-FILM TRANSISTOR ARRAY MANUFACTURING METHOD, THIN-FILM TRANSISTOR ARRAY, AND DISPLAY DEVICE Public/Granted day:2013-05-30
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