Invention Grant
US08530961B2 Compatible vertical double diffused metal oxide semiconductor transistor and lateral double diffused metal oxide semiconductor transistor and manufacture method thereof
有权
兼容的垂直双扩散金属氧化物半导体晶体管和横向双扩散金属氧化物半导体晶体管及其制造方法
- Patent Title: Compatible vertical double diffused metal oxide semiconductor transistor and lateral double diffused metal oxide semiconductor transistor and manufacture method thereof
- Patent Title (中): 兼容的垂直双扩散金属氧化物半导体晶体管和横向双扩散金属氧化物半导体晶体管及其制造方法
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Application No.: US13384002Application Date: 2010-10-26
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Publication No.: US08530961B2Publication Date: 2013-09-10
- Inventor: Linchun Gui , Le Wang , Zhiyong Zhao , Lili He
- Applicant: Linchun Gui , Le Wang , Zhiyong Zhao , Lili He
- Applicant Address: CN
- Assignee: CSMC Technologies FAB1 Co., Ltd.
- Current Assignee: CSMC Technologies FAB1 Co., Ltd.
- Current Assignee Address: CN
- Agency: Ohlandt, Greeley, Ruggiero & Perle, L.L.P.
- Priority: CN200910209187 20091028
- International Application: PCT/CN2010/078121 WO 20101026
- International Announcement: WO2011/050712 WO 20110505
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/336

Abstract:
A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region, where the P+ region is in contact with the source.
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