Invention Grant
US08531002B2 Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits
有权
用于在半导体集成电路上制造高价值电感器的晶片级的装置和方法
- Patent Title: Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits
- Patent Title (中): 用于在半导体集成电路上制造高价值电感器的晶片级的装置和方法
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Application No.: US12899384Application Date: 2010-10-06
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Publication No.: US08531002B2Publication Date: 2013-09-10
- Inventor: Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
- Applicant: Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Andrei Papou
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Eugene C. Conser; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H01L27/08
- IPC: H01L27/08

Abstract:
An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.
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