Invention Grant
US08531873B2 Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation 有权
超低功耗SRAM单元电路,具有电源反馈环路,用于近阈值和次阈值操作

Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation
Abstract:
An SRAM memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch that has a storage node Q, a storage node QB, a supply node, and a ground node. The supply node is coupled via a gating device to a supply voltage and ground node is connected to ground. In addition, storage node Q is fed back via feedback loop into a control node of the gating device. In operation, writing into the memory cell may be carried out in a similar manner to dual port SRAM cells, utilizing one or two write circuitries and for writing into storage node Q and storage node QB respectively. Differently from standard SRAM cells, the feedback loop, by controlling the gating device is configured to weaken the write contention.
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