Invention Grant
US08531885B2 NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layers
失效
基于NAND的2T2b NOR闪存阵列，使用二极管连接到电池的源节点，使用最少数量的金属层进行尺寸减小
- Patent Title: NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layers
- Patent Title (中): 基于NAND的2T2b NOR闪存阵列，使用二极管连接到电池的源节点，使用最少数量的金属层进行尺寸减小
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Application No.: US13116002Application Date: 2011-05-26
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Publication No.: US08531885B2Publication Date: 2013-09-10
- Inventor: Fu-Chang Hsu , Peter Wung Lee
- Applicant: Fu-Chang Hsu , Peter Wung Lee
- Applicant Address: US CA San Jose
- Assignee: Aplus Flash Technology, Inc.
- Current Assignee: Aplus Flash Technology, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: G11C11/34
- IPC: G11C11/34
Abstract:
A NAND-based NOR flash memory array has a matrix of NAND-based NOR flash cells arranged in rows and columns. Every two adjacent NAND-based NOR flash cells in a column share a common source node which is connected to a common source line through a diode. The source line may be made of a metal layer and is in contact directly with the source node or through an ohmic contact to form a Schottky barrier diode. The source line may also be made of a polysilicon or metal layer and connected to the source node through a pillar-structured polysilicon diode and a conduction layer. The diode may also be formed in the source node by enclosing a P/N+ junction diode in a heavily N+ doped region of the source node.
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