An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.