Techniques are disclosed relating to maximizing utilization of memory systems within power constraints of the memory systems. In one embodiment, an integrated circuit may include multiple memory controllers and an arbitration unit. Each memory controller may be configured to generate requests to perform memory operations on one or more portions of memory. The arbitration unit may be configured to grant no more than a specified number of requests during a time window TW. In some embodiments, a voltage converter that supplies power to the memory system may be configured to supply power to perform no more than the specified number of requests during the time window TW. The arbitration unit may thus be used, in some embodiments, to ensure that the greatest possible number of the specified number of memory requests are granted during a given time window TW (without exceeding the specified number).