Invention Grant
- Patent Title: Annotation management for hierarchical designs of integrated circuits
- Patent Title (中): 集成电路分级设计的注释管理
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Application No.: US12562067Application Date: 2009-09-17
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Publication No.: US08533650B2Publication Date: 2013-09-10
- Inventor: Bogdan G. Arsintescu , Gilles S. C. Lamant
- Applicant: Bogdan G. Arsintescu , Gilles S. C. Lamant
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F15/04
Abstract:
A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating the annotation with the mirrored block hierarchy in computer readable storage media.
Public/Granted literature
- US20110066995A1 ANNOTATION MANAGEMENT FOR HIERARCHICAL DESIGNS OF INTEGRATED CIRCUITS Public/Granted day:2011-03-17
Information query
