Invention Grant
US08541274B1 Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation
有权
形成具有纳米线栅极结构的三维半导体器件的方法,其中在源极/漏极形成之后形成纳米线栅极结构
- Patent Title: Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation
- Patent Title (中): 形成具有纳米线栅极结构的三维半导体器件的方法,其中在源极/漏极形成之后形成纳米线栅极结构
-
Application No.: US13609828Application Date: 2012-09-11
-
Publication No.: US08541274B1Publication Date: 2013-09-24
- Inventor: Ruilong Xie , Xiuyu Cai, Jr. , Kangguo Cheng , Ali Khakifirooz
- Applicant: Ruilong Xie , Xiuyu Cai, Jr. , Kangguo Cheng , Ali Khakifirooz
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial gate structure and removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin. The method also includes the steps of performing a fin reflow process on the exposed portions of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration and forming a replacement gate structure in the gate cavity and at least partially around the nanowire structure.
Information query
IPC分类: