- Patent Title: Semiconductor memory device including multi-layer gate structure
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Application No.: US13653060Application Date: 2012-10-16
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Publication No.: US08541827B2Publication Date: 2013-09-24
- Inventor: Toshitake Yaegashi
- Applicant: Toshitake Yaegashi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2001-352020 20011116; JP2002-156982 20020530
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/76 ; H01L29/94 ; H01L31/119
Abstract:
A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.
Public/Granted literature
- US20130037875A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE Public/Granted day:2013-02-14
Information query
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