Invention Grant
- Patent Title: Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same
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Application No.: US12816771Application Date: 2010-06-16
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Publication No.: US08541832B2Publication Date: 2013-09-24
- Inventor: Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
- Applicant: Ji-Young Kim , Kang L. Wang , Yong-Jik Park , Jeong-Hee Han , Augustin Jinwoo Hong
- Applicant Address: KR US CA Oakland
- Assignee: Samsung Electronics Co., Ltd.,The Regents of the University of California
- Current Assignee: Samsung Electronics Co., Ltd.,The Regents of the University of California
- Current Assignee Address: KR US CA Oakland
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2009-0121107 20091208
- Main IPC: H01L29/792
- IPC: H01L29/792

Abstract:
An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.
Public/Granted literature
- US20110018051A1 Integrated Circuit Memory Devices Having Vertical Transistor Arrays Therein and Methods of Forming Same Public/Granted day:2011-01-27
Information query
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