Invention Grant
US08541886B2 Integrated circuit packaging system with via and method of manufacture thereof
有权
具有通孔及其制造方法的集成电路封装系统
- Patent Title: Integrated circuit packaging system with via and method of manufacture thereof
- Patent Title (中): 具有通孔及其制造方法的集成电路封装系统
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Application No.: US12720667Application Date: 2010-03-09
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Publication No.: US08541886B2Publication Date: 2013-09-24
- Inventor: Chee Keong Chin
- Applicant: Chee Keong Chin
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Agent I-Chang John Yang
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L23/02 ; H01L23/495
Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing a stacking carrier having a cavity; placing a base integrated circuit in the cavity, the base integrated circuit having a base interconnect facing the cavity; mounting a stack integrated circuit to the base integrated circuit; and picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier.
Public/Granted literature
- US20110221072A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VIA AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2011-09-15
Information query
IPC分类:
