Invention Grant
- Patent Title: Semiconductor device and system
- Patent Title (中): 半导体器件和系统
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Application No.: US12755119Application Date: 2010-04-06
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Publication No.: US08542041B2Publication Date: 2013-09-24
- Inventor: Mitsuhiro Ogai , Hirokazu Yamazaki , Keizo Morita , Kazuaki Yamane , Yasuhiro Fujii , Kazuaki Takai , Shoichiro Kawashima
- Applicant: Mitsuhiro Ogai , Hirokazu Yamazaki , Keizo Morita , Kazuaki Yamane , Yasuhiro Fujii , Kazuaki Takai , Shoichiro Kawashima
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2009-092145 20090406
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.
Public/Granted literature
- US20100253419A1 SEMICONDUCTOR DEVICE AND SYSTEM Public/Granted day:2010-10-07
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