Invention Grant
- Patent Title: Double edge triggered flip flop
- Patent Title (中): 双边触发触发器
-
Application No.: US13150322Application Date: 2011-06-01
-
Publication No.: US08542048B2Publication Date: 2013-09-24
- Inventor: Ravindraraj Ramaraju
- Applicant: Ravindraraj Ramaraju
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent James L. Clingan, Jr.; Mary Jo Bertani
- Main IPC: H03K3/289
- IPC: H03K3/289

Abstract:
A dual edge triggered flip flop circuit uses clock signals that are delayed from a first clock signal and from one another by respective intervals. A first set of the plurality of clock signals are used to operate a first latch circuit to allow first data to be conducted to a storage element for a period of time after a rising edge of a first clock signal. The clock signals are further used to operate a second latch circuit to allow second data to be conducted to the storage element for a period of time after a falling edge of the first clock signal.
Public/Granted literature
- US20120306556A1 DOUBLE EDGE TRIGGERED FLIP FLOP Public/Granted day:2012-12-06
Information query
IPC分类: