Invention Grant
US08542142B2 Interleaved analog to digital converter with reduced number of multipliers for digital equalization 有权
具有数字均衡的乘法器数量减少的交错模数转换器

Interleaved analog to digital converter with reduced number of multipliers for digital equalization
Abstract:
A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.
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