A memory device comprising: a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor; a plurality of word lines, each word line connecting MRAM cells along a row via the gate of their select transistor; a plurality of bit lines, each bit line connecting MRAM cells along a column, each bit line connecting the MRAM cells via the drain of their select transistor; wherein the memory device further comprises a plurality of source lines, each source line connecting MRAM cells along a row; and wherein each source line connecting the MRAM cells via the other end of the magnetic tunnel junction.