A method of sample rate conversion and clock synchronization for multiple asynchronous input signals using a single processing core. A sample processing clock with a frequency equal to or higher than the input signal clock frequencies is provided. The clock period is divided into a number of time slots corresponding to the input signals. For each valid sample of an input signal, the core performs a first stage processing operation on the sample. Subsequently, for each required sample of an output signal, the core performs a second stage processing operation to generate the output sample.