A memory control apparatus includes memory control sections that read and write data from and to the DRAMs. The memory control sections periodically refresh the DRAMs. The refresh rate is set to avoid the conflict of the refresh operations as well as read and write operations that consume high power. A memory control method includes connecting memories in a memory control section where the memories perform periodic refresh and perform data write, data read, and refresh operations. Refresh commands are issued at optimum intervals and with arbitrary timing such that commands that consume high power do not conflict with each other.