A circuit for detecting and recording chip fails according to one embodiment of the present invention comprises a common error bus, a plurality of fail detector modules and a control center. Each of the plurality of fail detector modules is configured to receive at least a data signal to determine an occurrence of a chip fail and to correspondingly broadcast a fail code on the common error bus when the common error bus is not busy. The control center is configured to record a fail code from the common error bus and to report the recorded fail code when required.