Invention Grant
- Patent Title: Method and apparatus for partitioning programs to balance memory latency
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Application No.: US10585680Application Date: 2005-12-17
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Publication No.: US08543992B2Publication Date: 2013-09-24
- Inventor: Xiaodan Jiang , Jinquan Dai
- Applicant: Xiaodan Jiang , Jinquan Dai
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent L. Cho
- International Application: PCT/CN2005/002232 WO 20051217
- International Announcement: WO2007/068148 WO 20070621
- Main IPC: G06F9/45
- IPC: G06F9/45
Abstract:
A method of compiling code that includes partitioning instructions in the code among a plurality of processors based on memory access latency associated with the instructions is disclosed. According to one aspect of the invention, partitioning instructions includes partitioning memory access dependence chains. Other embodiments are described and claimed.
Public/Granted literature
- US20090193405A1 Method and apparatus for partitioning programs to balance memory latency Public/Granted day:2009-07-30
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