Invention Grant
- Patent Title: Method for eliminating defects from semiconductor materials
- Patent Title (中): 消除半导体材料缺陷的方法
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Application No.: US12368517Application Date: 2009-02-10
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Publication No.: US08545621B2Publication Date: 2013-10-01
- Inventor: Joseph Reid Henrichs
- Applicant: Joseph Reid Henrichs
- Applicant Address: US MO Lees Summit
- Assignee: OPC Laser Systems LLC
- Current Assignee: OPC Laser Systems LLC
- Current Assignee Address: US MO Lees Summit
- Main IPC: C30B33/00
- IPC: C30B33/00

Abstract:
Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvins for a period of ninety-six hours. At these low temperatures, alloys such as GaAs, InP, and GaP will form dipole molecular moments, which will re-align along lines of internal magnetic force as molecular bonds condense. Next the substrate wafer's temperature is ramped up to room temperature over a period of twenty-four hours. Next, the temperature of the substrate wafer is ramped up to assure that the temperature gradients made to occur within the wafer are kept low. Typically, a temper ramp up temperature will range between 300° F. to 1100° F. and depends upon the single crystal material used to construct the substrate wafer. Next, the substrate wafer undergoes a temper hold segment, which assures that the entire substrate wafer has had the benefit of the tempering temperature. A typical temper hold segment is around 3 hours and depends upon the material, thickness, and diameter size of the substrate wafer.
Public/Granted literature
- US20090162948A1 METHOD FOR ELIMINATING DEFECTS FROM SEMICONDUCTOR MATERIALS Public/Granted day:2009-06-25
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