Invention Grant
US08546195B2 Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor
有权
具有具有内部垂直互连结构的半导体管芯的半导体封装及其方法
- Patent Title: Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor
- Patent Title (中): 具有具有内部垂直互连结构的半导体管芯的半导体封装及其方法
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Application No.: US13335631Application Date: 2011-12-22
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Publication No.: US08546195B2Publication Date: 2013-10-01
- Inventor: Byung Tai Do , Seng Guan Chow , Heap Hoe Kuan , Linda Pei Ee Chua , Rui Huang
- Applicant: Byung Tai Do , Seng Guan Chow , Heap Hoe Kuan , Linda Pei Ee Chua , Rui Huang
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/485
- IPC: H01L23/485

Abstract:
A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps.
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