Invention Grant
- Patent Title: Top-down nanowire thinning processes
- Patent Title (中): 自上而下的纳米线稀疏过程
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Application No.: US12417936Application Date: 2009-04-03
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Publication No.: US08546269B2Publication Date: 2013-10-01
- Inventor: Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
- Applicant: Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Vazken Alexanian; Michael J. Chang, LLC
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L21/461 ; H01L29/06

Abstract:
Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.
Public/Granted literature
- US20100255680A1 Top-Down Nanowire Thinning Processes Public/Granted day:2010-10-07
Information query
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