Invention Grant
- Patent Title: Off-set top pixel electrode configuration
- Patent Title (中): 偏置顶级像素电极配置
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Application No.: US12990198Application Date: 2009-04-27
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Publication No.: US08546807B2Publication Date: 2013-10-01
- Inventor: Tim Von Werne , Kieran Reynolds , Boon Hean Pui
- Applicant: Tim Von Werne , Kieran Reynolds , Boon Hean Pui
- Applicant Address: GB
- Assignee: Plastic Logic Limited
- Current Assignee: Plastic Logic Limited
- Current Assignee Address: GB
- Agency: Knobbe Martens Olson & Bear LLP
- Priority: GB0807767.9 20080428; GB0901970.4 20090209
- International Application: PCT/GB2009/050423 WO 20090427
- International Announcement: WO2009/133388 WO 20091105
- Main IPC: H01L51/52
- IPC: H01L51/52 ; H01L51/56
Abstract:
A semiconductor device architecture where the top pixel electrode is deposited in an off-set configuration, such as to overlap the COM electrode, and also the gate electrode of the neighboring device.
Public/Granted literature
- US20110101361A1 OFF-SET TOP PIXEL ELECTRODE CONFIGURATION Public/Granted day:2011-05-05
Information query
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