Invention Grant
US08546865B2 Nonvolatile memory device having stacked semiconductor layers and common source line adjacent to bit line plug
有权
具有层叠半导体层和与位线插头相邻的公共源极线的非易失性存储器件
- Patent Title: Nonvolatile memory device having stacked semiconductor layers and common source line adjacent to bit line plug
- Patent Title (中): 具有层叠半导体层和与位线插头相邻的公共源极线的非易失性存储器件
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Application No.: US13218715Application Date: 2011-08-26
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Publication No.: US08546865B2Publication Date: 2013-10-01
- Inventor: Jong-Ho Lim , Choong-Ho Lee , Hye-Jin Cho
- Applicant: Jong-Ho Lim , Choong-Ho Lee , Hye-Jin Cho
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Stanzione & Kim, LLP
- Priority: KR10-2008-0059759 20080624
- Main IPC: H01L29/788
- IPC: H01L29/788 ; G11C11/34

Abstract:
Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.
Public/Granted literature
- US20110310665A1 Nonvolatile Memory Device Public/Granted day:2011-12-22
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