Invention Grant
- Patent Title: DRAM and memory array
- Patent Title (中): DRAM和存储器阵列
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Application No.: US12191315Application Date: 2008-08-14
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Publication No.: US08547729B2Publication Date: 2013-10-01
- Inventor: Wen-Kuei Huang
- Applicant: Wen-Kuei Huang
- Applicant Address: TW Taoyuan
- Assignee: Nanya Technology Corporation
- Current Assignee: Nanya Technology Corporation
- Current Assignee Address: TW Taoyuan
- Agency: Jianq Chyun IP Office
- Priority: TW97113488A 20080414
- Main IPC: G11C11/24
- IPC: G11C11/24

Abstract:
A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction, and the word lines are disposed on the bit lines in a second direction. Each recess channel is in the substrate between two bit lines below the word line, and each conductive plug connects each recess channel and the word lines. Each trench capacitor is disposed in the substrate between two bit lines where the recess channels are not formed. Because the word lines can be electrically connected with the recess channels directly without using an additional chip area, the WL access time can be accelerated without an increase of the chip size.
Public/Granted literature
- US20090257262A1 DRAM AND MEMORY ARRAY Public/Granted day:2009-10-15
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