Invention Grant
- Patent Title: Nor logic word line selection
- Patent Title (中): 也不是逻辑字线选择
-
Application No.: US12928989Application Date: 2010-12-22
-
Publication No.: US08547777B2Publication Date: 2013-10-01
- Inventor: Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
- Applicant: Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G11C8/08
- IPC: G11C8/08 ; G11C8/10 ; G11C8/02
Abstract:
A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
Public/Granted literature
- US20120163115A1 Nor logic word line selection Public/Granted day:2012-06-28
Information query
