An information processor includes processing units each processes an out-of-order memory access and includes a cache memory, an instruction port that holds instructions for accessing data in the cache memory, a first determinator that validates a first flag when a request for invalidating cache data is received after a target data of a load instruction is transferred from the cache memory and a load instruction having a cache index identical to that of a target address of the received invalidating instruction exists, a second determinator that validates a second flag when the target data of the load instruction in the instruction port is transferred after a cache miss of the target data occurred, and a re-execution determinator that instructs to re-execute an instruction that follows the load instruction if the first and the second flags are valid when a load instruction in the instruction port has been completed.