Invention Grant
- Patent Title: Non-volatile memory error mitigation
- Patent Title (中): 非易失性存储器错误减轻
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Application No.: US13175459Application Date: 2011-07-01
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Publication No.: US08549380B2Publication Date: 2013-10-01
- Inventor: Ravi H Motwani
- Applicant: Ravi H Motwani
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; H03M13/00 ; H03M13/03

Abstract:
Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.
Public/Granted literature
- US20130007559A1 NON-VOLATILE MEMORY ERROR MITIGATION Public/Granted day:2013-01-03
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