Invention Grant
- Patent Title: System and method for circuit design floorplanning
- Patent Title (中): 电路设计布局规划的系统和方法
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Application No.: US13013654Application Date: 2011-01-25
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Publication No.: US08549456B2Publication Date: 2013-10-01
- Inventor: Sanghamitra Roy , Koushik Chakraborty , Yiding Han
- Applicant: Sanghamitra Roy , Koushik Chakraborty , Yiding Han
- Applicant Address: US UT Logan
- Assignee: Utah State University
- Current Assignee: Utah State University
- Current Assignee Address: US UT Logan
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Circuit floorplanning is performed on a combination central processing unit and multiprocessor. A B*-tree data structure of a floorplan and circuit related constants reside in a central processing unit data storage. The B* tree structure of a floorplan along and said circuit related constants are copied to a multiprocessor data storage where multiple thread blocks, each consisting of a single thread, copy the tree to their own shared memories. The multiprocessor concurrently evaluates different moves in different thread blocks. The multiprocessor then evaluates objective function results and stores those results. The best result for floorplanning is selected from the multiple circuit evaluations.
Public/Granted literature
- US20110185328A1 System and Method for Circuit Design Floorplanning Public/Granted day:2011-07-28
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