Invention Grant
- Patent Title: Reduction of forming voltage in semiconductor devices
- Patent Title (中): 降低半导体器件中的形成电压
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Application No.: US12391784Application Date: 2009-02-24
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Publication No.: US08551809B2Publication Date: 2013-10-08
- Inventor: Pragati Kumar , Yun Wang , Prashant Phatak , Tony P. Chiang
- Applicant: Pragati Kumar , Yun Wang , Prashant Phatak , Tony P. Chiang
- Applicant Address: US CA San Jose
- Assignee: Intermolecular, Inc.
- Current Assignee: Intermolecular, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L47/00
- IPC: H01L47/00 ; H01L29/06 ; H01L21/00 ; H01L21/16

Abstract:
A nonvolatile memory device and methods of manufacturing the same has one electrode with a higher work function and a second electrode with a lower work function. The nonvolatile memory device further comprises one or more resistive random access memory (RRAM) cells. The RRAM cells comprise a semiconductor layer with a bandgap of at least four electron volts and a barrier layer between the semiconductor layer and one of the electrodes.
Public/Granted literature
- US20090272962A1 REDUCTION OF FORMING VOLTAGE IN SEMICONDUCTOR DEVICES Public/Granted day:2009-11-05
Information query
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