Invention Grant
- Patent Title: Wafer level IC assembly method
- Patent Title (中): 晶圆级IC组装方法
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Application No.: US13554580Application Date: 2012-07-20
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Publication No.: US08551813B2Publication Date: 2013-10-08
- Inventor: Chien Hsiun Lee , Clinton Chao , Mirng Ji Lii , Tjandra Winata Karta
- Applicant: Chien Hsiun Lee , Clinton Chao , Mirng Ji Lii , Tjandra Winata Karta
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Novak Druce Connolly Bove + Quigg LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.
Public/Granted literature
- US20120288998A1 WAFER LEVEL IC ASSEMBLY METHOD Public/Granted day:2012-11-15
Information query
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