Invention Grant
- Patent Title: Method of producing precision vertical and horizontal layers in a vertical semiconductor structure
- Patent Title (中): 在垂直半导体结构中生产精密垂直和水平层的方法
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Application No.: US13458310Application Date: 2012-04-27
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Publication No.: US08551834B2Publication Date: 2013-10-08
- Inventor: Jonas Ohlsson , Lars Samuelson , Erik Lind , Lars-Erik Wernersson , Truls Lowgren
- Applicant: Jonas Ohlsson , Lars Samuelson , Erik Lind , Lars-Erik Wernersson , Truls Lowgren
- Applicant Address: SE Lund
- Assignee: QuNano AB
- Current Assignee: QuNano AB
- Current Assignee Address: SE Lund
- Agency: The Marbury Law Group PLLC
- Priority: SE0601997 20060918; SE0701885 20070817
- Main IPC: H01L21/76
- IPC: H01L21/76
Abstract:
The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.
Public/Granted literature
- US20120211727A1 Method of Producing Precision Vertical and Horizontal Layers in a Vertical Semiconductor Structure Public/Granted day:2012-08-23
Information query
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